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题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns module sequence_test2( input wire clk , input wire rst , &...

2022-06-02

0 289

题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns module width_8to12( input &n...

2022-06-02

0 276

题解 | #数据串转并电路#

`timescale 1ns/1ns module s_to_p( input &...

2022-06-02

0 240

题解 | #不重叠序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data,...

2022-06-01

0 247

题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [3:0] curr_state; reg [3:0] next_state; always @ (...

2022-06-01

0 264

题解 | #多功能数据处理器#

`timescale 1ns/1ns module data_select( input clk, input rst_n, input signed[7:0]a, input signed[7:0]b, input [1:0]select, output reg signed [8:0]c ); ...

2022-05-24

0 245