题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
 reg [8:0]buff;
 always@(posedge clk or negedge rst_n)
 begin if(!rst_n)
 buff<=9'b0;
 else buff<={buff[7:0],a};
 end

  always@(posedge clk or negedge rst_n)
 begin if(!rst_n)
 match<=0;
 else if((buff[8:6]==3'b011)&(buff[2:0]==3'b110))
 match<=1;
 else match<=0;
 end 
endmodule