题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
parameter	s0	=	4'b0000,
			s1	=	4'b0001,
			s2	=	4'b0010,
			s3	=	4'b0100,
			s4	=	4'b1000;

reg	[3:0]	cur_state,nxt_state;

always@(posedge	clk or negedge rst)
	if(!rst)
		cur_state	<=	s0;
	else	
		cur_state	<=	nxt_state;

always@(*)	begin
	if(!rst)
		nxt_state	<=	s0;
	else	case(cur_state)	
		s0:begin
			if(data==1'b1)
				nxt_state	<=	s1;
			else
				nxt_state	<=	s0;
		end
		s1:begin
			if(data==1'b1)
				nxt_state	<=	s2;
			else
				nxt_state	<=	s1;
		end
		s2:begin
			if(data==1'b1)
				nxt_state	<=	s3;
			else
				nxt_state	<=	s2;			
		end	
		s3:begin
			if(data==1'b1)
				nxt_state	<=	s4;
			else
				nxt_state	<=	s3;			
		end
		s4:begin
			if(data==1'b1)
				nxt_state	<=	s1;
			else
				nxt_state	<=	s0;			
		end
	default:	nxt_state	<=	s0;
	endcase	
end

always@(*)	begin
	if(!rst)
		flag	<=	1'b0;
	else	case(cur_state)
		s4:begin
				flag	<=	1'b1;
		end
	default	:	flag	<=	1'b0;
	endcase
end




//*************code***********//
endmodule