题解 | 整数倍数据位宽转换8to16

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

reg cnt;
reg [7:0] r_reg;

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		cnt <= 'd0;
	else if(valid_in)
		cnt <= ~cnt;
	else 
		cnt <= cnt;
end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		r_reg <= 'd0;
	else if(valid_in)
		r_reg <= data_in;
	else 
		r_reg <= r_reg;
end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		valid_out <= 'd0;
	else if(cnt && valid_in)
		valid_out <= 'd1;
	else 
		valid_out <= 'd0;
end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		data_out <= 'd0;
	else if(cnt && valid_in)
		data_out <= {r_reg,data_in};
	else 
		data_out <= data_out;
end
endmodule