题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);
reg [3:0] num_tmp;
always @ (posedge clk or negedge rst_n) 
begin
    if(~rst_n) begin
        num_tmp <= 4'b0;
    end 
    else begin
        if(mode == 1'b1) begin
            if(num_tmp == 4'd9)
                num_tmp <= 4'd0;
            else 
                num_tmp <= num_tmp + 4'd1;
        end 
        else begin
            if(num_tmp == 4'd0)
                num_tmp <= 4'd9;
            else
                num_tmp <= num_tmp - 4'd1;
        end 
    end 
end 

always @ (posedge clk or negedge rst_n) 
begin
    if(~rst_n) begin
        number <= 4'b0;
    end 
    else begin
        number <= num_tmp;
    end 
end 

always @ (posedge clk or negedge rst_n) 
begin
    if(~rst_n) begin
        zero <= 1'b0;
    end 
    else begin
        zero <= (num_tmp == 4'b0);
    end 
end 
endmodule