````timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [1:0] cnt;
reg [7:0] d_r;
always @(posedge clk or negedge rst) begin
if(!rst) begin
cnt <= 2'b0;
end
else begin
cnt <= cnt + 2'd1;
end
end
always @(posedge clk or negedge rst) begin
if(!rst) begin
out <= 0;
input_grant <= 0;
d_r <= 0;
end
else begin
case (cnt)
2'd0 : begin
out <= d;
d_r <= d;
input_grant <= 1'b1;
end
2'd1 : begin
out <= {3'b0,d_r} + ({3'b0,d_r}<<1);
input_grant <= 1'b0;
end
2'd2 : begin
out <= {3'b0,d_r} + ({3'b0,d_r}<<1) + ({3'b0,d_r}<<2);
end
2'd3 : begin
out <= {3'b0,d_r}<<3;
end
default : begin
out <= 0;
input_grant <= 0;
end
endcase
end
end
always @(posedge clk or negedge rst) begin
if(!rst) begin
end
end
//*************code***********//
endmodule