题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
integer i;
reg [3:0]buff[127:0];
always@(posedge clk or negedge rst)begin 
 if(!rst)
 begin for(i=0;i<128;i=i+1)
    buff[i]<=0;
 end
   else if(enb)
    buff[addr]<=w_data;
end
assign r_data=(!enb)? buff[addr]:0;
//*************code***********//
endmodule