题解 | #实现3-8译码器①#

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);

assign Y0_n=~(~A2&~A1&~A0&E3&~E2_n&~E1_n);
assign Y1_n=~(~A2&~A1&A0&E3&~E2_n&~E1_n);
assign Y2_n=~(~A2&A1&~A0&E3&~E2_n&~E1_n);
assign Y3_n=~(~A2&A1&A0&E3&~E2_n&~E1_n);
assign Y4_n=~(A2&~A1&~A0&E3&~E2_n&~E1_n);
assign Y5_n=~(A2&~A1&A0&E3&~E2_n&~E1_n);
assign Y6_n=~(A2&A1&~A0&E3&~E2_n&~E1_n);
assign Y7_n=~(A2&A1&A0&E3&~E2_n&~E1_n);




endmodule