题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg clkn;
reg clkp;
reg [2:0]cntn;
reg [2:0]cntp;
always@(negedge  clk_in or  posedge rst)
begin 
    if(!rst)
    cntn<=0;
    else if(cntn==6)
    cntn<=0;
    else cntn<=cntn+1;
end
always@(negedge  clk_in or  posedge rst)
begin 
    if(!rst)
    clkn<=0;
    else if(cntn<3)
    clkn<=0;
    else clkn<=1;
end 

always@(posedge  clk_in or  posedge rst)
begin 
    if(!rst)
    cntp<=0;
    else if(cntp==6)
    cntp<=0;
    else cntp<=cntp+1;
end
always@(posedge  clk_in or  posedge rst)
begin 
    if(!rst)
    clkp<=0;
    else if(cntp<3)
    clkp<=0;
    else clkp<=1;
end 

assign clk_out7=clkn&clkp;


//*************code***********//
endmodule