题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
parameter S0 = 5'b00001;
parameter S1 = 5'b00010;
parameter S2 = 5'b00100;
parameter S3 = 5'b01000;
parameter S4 = 5'b10000;

reg [4:0] cs, ns;
always @ (posedge clk or negedge rst) 
begin
    if( ~rst ) begin
        cs <= S0;
    end 
    else begin
        cs <= ns;
    end 
end 

always @ (*) 
begin
    case(cs) 
        S0 : ns = (data == 1'b1) ? S1 : S0;
        S1 : ns = (data == 1'b1) ? S2 : S1;
        S2 : ns = (data == 1'b1) ? S3 : S2;
        S3 : ns = (data == 1'b1) ? S4 : S3;
        S4 : ns = (data == 1'b1) ? S1 : S0;
        default : ns = S0;
    endcase
end 

always @ (*) 
begin
    flag = (cs == S4);
end 
//assign flag = (cs == S4);

//*************code***********//
endmodule