题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
reg [1:0] cnt;
reg [7:0]buff;
always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n)
	cnt<=0;
	else if(valid_in)
	 if(cnt==2)
	 cnt<=0;
	 else cnt<=cnt+1;
end
always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n)
	begin buff<=0;
	data_out<=0; end 
	else if(valid_in)begin
	if(cnt==1)
	begin buff[3:0]<=data_in[3:0];
	     data_out<={buff,data_in[7:4]};end
	if (cnt==2)
	 begin 
	     data_out<={buff[3:0],data_in};end
	else begin buff<=data_in; 
	 end
end
end
always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n)
	valid_out<=0;
	else if(valid_in&((cnt==1)|(cnt==2)))
	valid_out<=1;
	else valid_out<=0;
end
endmodule