题解 | #数据累加输出#(时序分析)

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

reg [2:0] cnt_in ;

// cnt_in 
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	    cnt_in <= 'd0           ;
    else if(cnt_in == 'd4 && (valid_a && ready_a))
	    cnt_in <= 'd1           ; 
    else if(valid_a && ready_a)
	    cnt_in <= cnt_in + 1'b1 ;
end

assign ready_a = ((cnt_in <= 'd3)|(cnt_in == 'd4 && ready_b)) ?1'b1:1'b0 ;

// valid_b
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	    valid_b <= 1'b0    ;
    else if(valid_b && ready_b)
	    valid_b <= 1'b0    ;
	else if(cnt_in == 'd3 && valid_a && ready_a)
	    valid_b <= 1'b1    ;
end

// data_out 
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	    data_out <= 'd0                ;
	else if(cnt_in <= 'd3 && valid_a && ready_a)
	    data_out <= data_out + data_in ; 
	else if(cnt_in == 'd4 && (valid_a && ready_a))
	    data_out <= data_in            ;
end

endmodule