序列缓存对比法

timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
    
    reg [8:0]data_comp;
    
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            data_comp <= 9'd0;
            match <= 1'b0;
        end
        else begin
            data_comp <= {data_comp[7:0],a};
            if((data_comp[8:6] == 3'b011)&&(data_comp[2:0] == 3'b110))begin
                match <= 1'b1;
            end
            else
                match <= 1'b0;
        end
    end
  
endmodule