`timescale 1ns/1ns module seller2( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire sel , output reg out1, output reg out2, output reg out3 ); //*************code***********// reg [2:0] money;//0.5Y = 001,1Y=010, always@(posedge clk or negedge rst) if(!rst) money <= 3'd0; else if((!sel && money>=3) || (sel && money>=5)) money <= 3'd0; else if(d1) money <= money + 1; else if(d2) money <= money + 2; else money <= money; //output always@(posedge clk or negedge rst) if(!rst) begin out1 <= 1'b0; out2 <= 1'b0; out3 <= 1'b0; end else if(!sel && money>=3) begin out1 <= 1'b1; out2 <= 1'b0; out3 <= money - 3'd3; end else if(sel && money>=5) begin out1 <= 1'b0; out2 <= 1'b1; out3 <= money - 3'd5; end else begin out1 <= 1'b0; out2 <= 1'b0; out3 <= 1'b0; end //*************code***********// endmodule