`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output [8:0] c
	);
wire[8:0]c0,c1;
reg [8:0]c_reg;
mul u0(
	.clk(clk),
	.rst_n(rst_n),
	.a(a),
	.b(12),
	.c(c0)
);
mul u1(
	.clk(clk),
	.rst_n(rst_n),
	.a(b),
	.b(5),
	.c(c1)
);
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		c_reg<=0;
	end
	else begin
		c_reg<=c0+c1;
	end
end
assign c=c_reg;
endmodule

module mul(
	input clk,
	input rst_n,
	input [3:0]a,
	input [3:0]b,
	output reg[8:0]c

);
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		c<=0;
	end
	else begin
		case(b)
		4'b0000:c<=0;
		4'b0001:c<=a;
		4'b0010:c<={a,1'b0};
		4'b0011:c<={a,1'b0}+a;
		4'b0100:c<={a,2'b0};
		4'b0101:c<={a,2'b0}+a;
		4'b0110:c<={a,2'b0}+{a,1'b0};
		4'b0111:c<={a,2'b0}+{a,1'b0}+a;
		4'b1000:c<={a,3'b0};
		4'b1001:c<={a,3'b0}+a;
		4'b1010:c<={a,3'b0}+{a,1'b0};
		4'b1011:c<={a,3'b0}+{a,1'b0}+a;
		4'b1100:c<={a,3'b0}+{a,2'b0};
		4'b1101:c<={a,3'b0}+{a,2'b0}+a;
		4'b1110:c<={a,3'b0}+{a,2'b0}+{a,1'b0};
		4'b1111:c<={a,3'b0}+{a,2'b0}+{a,1'b0}+a;
		default:c<=0;
		endcase
	end

end
endmodule