`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg [3:0] d0,d1,d2,d3;

always@(posedge clk or negedge rst)
    if(!rst)
        begin
            d0  <=  4'd0;
            d1  <=  4'd0;
            d2  <=  4'd0;
            d3  <=  4'd0;
        end
    else    if(sel==2'd0)
        begin
            d0  <=  d[3:0];
            d1  <=  d[7:4];
            d2  <=  d[11:8];
            d3  <=  d[15:12];
        end

assign  out = (sel==2'd3)? (d0+d3):(sel==2'd2)? (d0+d2):(sel==2'd1)? (d0+d1):5'd0;
assign  validout = (sel==2'd0)? 1'b0:1'b1;    


//*************code***********//
endmodule