题解 | #位拆分与运算#

````timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg [4:0] out_r;
reg validout_r;
reg [15:0]d_r;
always @(posedge clk or negedge rst) begin
    if(!rst) begin
        d_r <= 'b0;
    end
    else if(~(|sel))begin
        d_r <= d;
    end
end
always @(posedge clk or negedge rst) begin
    if(!rst) begin
        out_r <= 'b0;
        validout_r <= 'b0;
    end
    else begin
        case (sel)
           2'd1 : begin
            out_r <= d_r[3:0] + d_r[7:4];
            validout_r <= 'b1;
           end

           2'd2 : begin
            out_r <= d_r[3:0] + d_r[11:8];
            validout_r <= 'b1;
           end

           2'd3 : begin
            out_r <= d_r[3:0] + d_r[15:12];
            validout_r <= 'b1;
           end

           default: begin
            out_r <= 'b0;
            validout_r <= 'b0;
           end
        endcase

    end
end

assign out = (|sel)?out_r:'b0;
assign validout = validout_r;

//*************code***********//
endmodule