题解 | #数据选择器实现逻辑电路#

`timescale 1ns/1ns

module data_sel(
   input             S0     ,
   input             S1     ,
   input             D0     ,
   input             D1     ,
   input             D2     ,
   input             D3     ,
   
   output wire        Y    
);

assign Y = ~S1 & (~S0&D0 | S0&D1) | S1&(~S0&D2 | S0&D3);
     
endmodule

module sel_exp(
   input             A     ,
   input             B     ,
   input             C     ,
   
   output wire       L            
);
wire Y1,Y2,Y3;

data_sel uut1 (
    .S0(B),
    .S1(A),
    .D0(0),
    .D1(0),
    .D2(0),
    .D3(1),
    .Y(Y1)
);
data_sel uut2 (
    .S0(A),
    .S1(C),
    .D0(0),
    .D1(1),
    .D2(0),
    .D3(0),
    .Y(Y2)
);
data_sel uut3 (
    .S0(C),
    .S1(B),
    .D0(0),
    .D1(0),
    .D2(0),
    .D3(1),
    .Y(Y3)
);
assign L=Y1|Y2|Y3;
endmodule