题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns
/*两段式*/
module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter idle=0,s0=1,s1=2,s2=3,s3=4,s4=5;
reg [2:0]cs,ns;
always@(posedge clk or negedge rst)begin
	if(!rst)cs<=idle;
	else cs<=ns;
end
always@(*)begin
	case(cs)
	idle: begin
		ns=data?s0:idle;
		flag=0;
	end
	s0:begin
		ns=data?s0:s1;
		flag=0;
	end
	s1:begin
		ns=data?s2:idle;
		flag=0;
	end
	s2:begin
		ns=data?s3:s1;
		flag=0;
	end
	s3:begin
		ns=data?s4:s1;
		flag=0;
	end
	s4:begin
		ns=data?s0:idle;
		flag=1;
	end
	default:begin
	ns=idle;flag=0;end
	endcase
end
//*************code***********//
endmodule