题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//

reg [2:0]  cnt  ;
reg [7:0] d_reg;




always@(posedge clk or negedge rst)begin
    if(!rst)
        cnt <= 'd0;
    else if(cnt == 'd3 )
        cnt <= 'd0;
    else
        cnt <= cnt + 1'b1;        
end
always@(posedge clk or negedge rst)begin
    if(!rst) begin
        out         <= 'd0 ;
        input_grant <= 1'b0;
    end
    else begin
        case(cnt)
            3'd0: begin
                 out         <= d    ;
                 input_grant <= 1'b1;
                 d_reg       <= d;
            end
            3'd1: begin
                 out         <= (d_reg<<2)-d_reg ;
                 input_grant <= 1'b0;
            end
            3'd2: begin
                 out         <= (d_reg<<3)-d_reg  ;
                 input_grant <= 1'b0;
            end
            3'd3: begin
                 out         <= (d_reg<<3) ;
                 input_grant <= 1'b0;
            end
            

            default:;
        endcase
    end
        
end
//*************code***********//
endmodule