题解 | #不重叠序列检测#

移位寄存器+计数器实现

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
    
    reg [2:0] cnt_seq;
    reg [5:0] reg_data;
    
    always@(posedge clk or negedge rst_n) begin: count_sequence
        if(~rst_n)
            cnt_seq <= 3'b0;
        else if(cnt_seq == 3'd5)
            cnt_seq <= 3'b0;
        else
            cnt_seq <= cnt_seq + 1;
    end
        
    always@(posedge clk or negedge rst_n) begin: register_data
        if(~rst_n)
            reg_data <= 6'b0;
        else
            reg_data <= {reg_data[4:0], data};
    end
    
    always@(posedge clk or negedge rst_n) begin:judge_match
        if(~rst_n) begin
            match <= 0;
            not_match <= 0;
        end
        else if(cnt_seq == 3'd5) begin
            if({reg_data[4:0], data} == 6'b011100) begin
                match <= 1;
                not_match <= 0;
            end
            else begin
                match <= 0;
                not_match <= 1;
            end
        end
        else begin
            match <= 0;
            not_match <= 0;
        end
    end
    
endmodule