`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);
wire [3:0]G;
wire [3:0]P;
    assign G[0] = A_in[0] & B_in[0];
	assign G[1] = A_in[1] & B_in[1];
	assign G[2] = A_in[2] & B_in[2];
	assign G[3] = A_in[3] & B_in[3];

	assign P[0] = A_in[0] ^ B_in[0];
	assign P[1] = A_in[1] ^ B_in[1];
	assign P[2] = A_in[2] ^ B_in[2];
	assign P[3] = A_in[3] ^ B_in[3];

wire [3:0] C;

	assign S[0] = P[0] ^ C_1;
	assign S[1] = P[1] ^ C[0];
	assign S[2] = P[2] ^ C[1];
	assign S[3] = P[3] ^ C[2];
	assign CO = C[3];

	assign C[0] = G[0] | P[0]&C_1;
	assign C[1] = G[1] | P[1]&C[0];
	assign C[2] = G[2] | P[2]&C[1];
	assign C[3] = G[3] | P[3]&C[2];
endmodule

这种写法是最基础的写法。

尝试用别的方法来写:

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);
wire [3:0]G;
wire [3:0]P;
	genvar gi;
	generate
		for(gi=0;gi<4;gi=gi+1)begin:G_module
			assign G[gi]=A_in[gi]&B_in[gi];
		end
	endgenerate

	genvar pi;
	generate
		for(pi=0;pi<4;pi=pi+1)begin:P_module
			assign P[pi]=A_in[pi]^B_in[pi];
		end
	endgenerate

wire [3:0] C;

	assign S[0] = P[0] ^ C_1;
	assign S[1] = P[1] ^ C[0];
	assign S[2] = P[2] ^ C[1];
	assign S[3] = P[3] ^ C[2];
	assign CO = C[3];

	assign C[0] = G[0] | P[0]&C_1;
	assign C[1] = G[1] | P[1]&C[0];
	assign C[2] = G[2] | P[2]&C[1];
	assign C[3] = G[3] | P[3]&C[2];
endmodule