题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);
reg [1:0]state;
reg [1:0]next_state;
always @(posedge clk or posedge rst_n)
if(rst_n==0) 
state<=2'b00;
else 
state<=next_state;
reg Y_reg;
always @(*)
begin 
    case (state)
    2'b00:begin if(C==1)
             begin  next_state=2'b01; Y_reg=0;     end 
             else begin next_state=2'b00;  Y_reg=0;end 
    end
    2'b01:begin if(C==1)
             begin next_state=2'b01;  Y_reg=0; end 
             else  begin next_state=2'b11;  Y_reg=0; end 
    end
    2'b10:begin if(C==1)
             begin next_state=2'b10;  Y_reg=1; end 
             else begin next_state=2'b00;  Y_reg=0; end 
    end
    2'b11:begin if(C==1)
             begin next_state=2'b10;  Y_reg=1; end 
             else begin next_state=2'b11;  Y_reg=1; end 
    end
    default : begin next_state=2'b00;  Y_reg=0; end 

    endcase
end
assign Y=Y_reg;
endmodule