题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
reg [3:0] cnt;
always @ (posedge clk or negedge rst_n) 
begin
    if( ~rst_n ) begin
        cnt <= 4'd0;
    end 
    else begin
        if( valid_in ) begin
            cnt <= cnt + 4'd1;
        end 
    end 
end

reg [15:0] data_reg;
reg [127:0] data_out_r;
always @ (posedge clk or negedge rst_n) 
begin
    if( ~rst_n ) begin
        data_out <= 128'b0;
        valid_out <= 1'b0;
        data_out_r <= 128'b0;
    end 
    else begin
        if(valid_in) begin
            case(cnt)
                4'd0 : begin
                    data_out_r[127:104] <= data_in;
                    valid_out <= 1'b0;
                end
                4'd1 : begin
                    data_out_r[103:80] <= data_in;
                    valid_out <= 1'b0;
                end
                4'd2 : begin
                    data_out_r[79:56] <= data_in;
                    valid_out <= 1'b0;
                end
                4'd3 : begin
                    data_out_r[55:32] <= data_in;
                    valid_out <= 1'b0;
                end
                4'd4 : begin
                    data_out_r[31:8] <= data_in;
                    valid_out <= 1'b0;
                end
                4'd5 : begin
                    data_out <= {data_out_r[127:8], data_in[23:16]};  //这段是什么意思
                    data_out_r[127:112] <= data_in[15:0];
                    valid_out <= 1'b1;
                end
                4'd6 : begin
                    data_out_r[111:88] <= data_in[23:0];
                    valid_out <= 1'b0;
                end
                4'd7 : begin
                    data_out_r[87:64] <= data_in[23:0];
                    valid_out <= 1'b0;
                end
                4'd8 : begin
                    data_out_r[63:40] <= data_in[23:0];
                    valid_out <= 1'b0;
                end
                4'd9 : begin
                    data_out_r[39:16] <= data_in[23:0];
                    valid_out <= 1'b0;
                end
                4'd10 : begin
                    data_out <= {data_out_r[127:16], data_in[23:8]};
                    data_out_r[127:120] <= data_in[7:0];
                    valid_out <= 1'b1;
                end
                4'd11 : begin
                    data_out_r[119:96] <= data_in[23:0];
                    valid_out <= 1'b0;
                end
                4'd12 : begin
                    data_out_r[95:72] <= data_in[23:0];
                    valid_out <= 1'b0;
                end
                4'd13 : begin
                    data_out_r[71:48] <= data_in[23:0];
                    valid_out <= 1'b0;
                end
                4'd14 : begin
                    data_out_r[47:24] <= data_in[23:0];
                    valid_out <= 1'b0;
                end
                4'd15 : begin
                    data_out_r[23:0] <= data_in[23:0];
                    data_out <= {data_out_r[127:24], data_in[23:0]};
                    valid_out <= 1'b1;
                end
            endcase
        end
        else begin
            valid_out <= 1'b0;
        end 
    end 
end

endmodule