`timescale 1ns/1ns module calculation( input clk, input rst_n, input [3:0] a, input [3:0] b, output [8:0] c ); wire [7:0] pro0,pro1; mult_4 u0 ( .clk (clk), .rst_n (rst_n), .data_a (4'd12), .data_b (a), .prod (pro0) ); mult_4 u1 ( .clk (clk), .rst_n (rst_n), .data_a (4'd5), .data_b (b), .prod (pro1) ); assign c = pro0 + pro1; endmodule module mult_4 ( input wire clk , input wire rst_n, input wire [3:0] data_a, input wire [3:0] data_b, output reg [7:0] prod ); reg [3:0] mul0,mul1,mul2,mul3; always@(posedge clk or negedge rst_n) if(!rst_n) begin mul0 <= 4'd0; mul1 <= 4'd0; mul2 <= 4'd0; mul3 <= 4'd0; end else begin mul0 <= data_b[0]? data_a:0; mul1 <= data_b[1]? data_a:0; mul2 <= data_b[2]? data_a:0; mul3 <= data_b[3]? data_a:0; end always@(posedge clk or negedge rst_n) if(!rst_n) prod <= 8'd0; else prod <= mul0 + (mul1 <<1) + (mul2 <<2) + (mul3 <<3); endmodule