题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
    
    reg a_r1;
    always@(posedge clk or negedge rst_n) begin:input_delay
        if(~rst_n) begin
            a_r1 <= 0;
        end
        else begin
            a_r1 <= a;
        end
    end
    
    always@(posedge clk or negedge rst_n) begin: gen_edge_detect
        if(~rst_n) begin
            rise <= 0;
            down <= 0;
        end
        else begin
            if(~a_r1 & a)
                rise <= 1;
            else
                rise <= 0;
            
            if(a_r1 & ~a)
                down <= 1;
            else
                down <= 0;
        end
    end
    
endmodule