题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);
wire ready_a;
 wire [7:0]bu;
 wire [7:0]fubu;
 assign fubu={data_in[7],~data_in[6:0]+1'b1};
 assign bu=data_in[7]?fubu: data_in;
 wire [9:0] kuo;
 assign kuo={bu[7],bu[7],bu[7],bu[7],bu};
 reg [2:0]cnt;
always@(posedge clk or negedge rst_n)begin 
	if(!rst_n)
	cnt<=0;
	else if(valid_b&ready_b)
	 cnt<=1;
	else if(valid_a&ready_a) //输入数据有效且本模块可以接收数据时，计数
	cnt<=cnt+1;
end

always@(posedge clk or negedge rst_n)
begin if(!rst_n)
begin  
      data_out<=0; 
      valid_b<=0;
end
else if(valid_a)
  if(ready_a) 
       if(ready_b&valid_b)
	    begin data_out<=kuo;
		valid_b<=0; end 
   else 
  begin  data_out<=data_out+kuo; 
   if(cnt==3)
	valid_b<=1;
	else valid_b<=0;
  end
  else begin data_out<=data_out;
             valid_b<=1; end
end
assign ready_a=(valid_b&(!ready_b))? 0:1;

endmodule