题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
reg [4:0]cnt;
always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n)
	cnt<=0;
	else  if(valid_in)
    begin     if(cnt==15)
      begin   cnt<=0; end 
        else 
  begin cnt<=cnt+1; end end 
end
reg [127:0] buff;

always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n)
	begin 
		buff<=0;
		data_out<=0;
	end
	else if(valid_in)begin 
	if(cnt==5)
	begin buff[127:112]<=data_in[15:0];
	       data_out<={buff[127:8],data_in[23:16]}; end
    if(cnt==10)
	begin buff[127:120]<=data_in[7:0];
	       data_out<={buff[127:16],data_in[23:8]}; end
	if(cnt==15)
	begin 
	       data_out<={buff[127:24],data_in}; end
    if(cnt==0)
	buff[127:104]<=data_in;
	if(cnt==1)
	buff[103:80]<=data_in;	
	if(cnt==2)
	buff[79:56]<=data_in;	
	if(cnt==3)
	buff[55:32]<=data_in;
	if(cnt==4)
	buff[31:8]<=data_in;	
    if(cnt==6)
	buff[111:88]<=data_in;
	if(cnt==7)
	buff[87:64]<=data_in;	
	if(cnt==8)
	buff[63:40]<=data_in;	
	if(cnt==9)
	buff[39:16]<=data_in;
    if(cnt==11)
	buff[119:96]<=data_in;
	if(cnt==12)
	buff[95:72]<=data_in;	
	if(cnt==13)
	buff[71:48]<=data_in;	
	if(cnt==14)
	buff[47:24]<=data_in;
end
    end
always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n)
	valid_out<=0;
	else if(valid_in&((cnt==5)|(cnt==10)|(cnt==15)))
	valid_out<=1;
	else valid_out<=0;
end
endmodule