题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
reg	[119:0]	data_reg;
reg	[5:0]	cnt;


always@(posedge clk or negedge rst_n)
	if(!rst_n)
		cnt	<=	6'd0;
	else	if(cnt==6'd15 && valid_in)
		cnt	<=	6'd0;
	else	if(valid_in)
		cnt	<=	cnt	+ 1'b1; 	//6个数据输出一次，后续5个数据输出一次X2


always@(posedge clk or negedge rst_n)
	if(!rst_n)
		valid_out	<=	1'b0;
	else	if(cnt==6'd5 && valid_in)
		valid_out	<=	1'b1;
	else	if(cnt==6'd10 && valid_in)
		valid_out	<=	1'b1;
	else	if(cnt==6'd15 && valid_in)
		valid_out	<=	1'b1;
	else
		valid_out	<=	1'b0;


always@(posedge clk or negedge rst_n)
	if(!rst_n)
		data_reg	<=	120'd0;
	else	if(cnt==6'd5 && valid_in)
		data_reg	<=	data_in[15:0];
	else	if(cnt==6'd10 && valid_in)
		data_reg	<=	data_in[7:0];
	else	if(cnt==6'd15 && valid_in)
		data_reg	<=	120'd0;
	else	if(valid_in)
		data_reg	<=	{data_reg[95:0],data_in};

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		data_out	<=	128'd0;
	else	if(cnt==6'd5 && valid_in)
		data_out	<={data_reg,data_in[23:16]};
	else	if(cnt==6'd10 && valid_in)
		data_out	<={data_reg[111:0],data_in[23:8]};
	else	if(cnt==6'd15 && valid_in)
		data_out	<={data_reg[103:0],data_in};
	else
		data_out	<=	data_out;







endmodule