`timescale 1ns/1ns
module calculation(
input clk,
input rst_n,
input [3:0] a,
input [3:0] b,
output [8:0] c
);
reg[8:0]c;
wire [8:0]out1,out2;
wire [3:0]t1=4'b1100;
wire [3:0]t2=4'b0101;
cheng cheng_uut1(
.in1(t1),
.clk(clk),
.rst_n(rst_n),
.in2(a),
.out(out1)
);
cheng cheng_uut2(
.in1(t2),
.clk(clk),
.rst_n(rst_n),
.in2(b),
.out(out2)
);
always@(posedge clk or negedge rst_n)
if(!rst_n)
c<=0;
else c<=out1+out2;
endmodule
module cheng(
input clk,
input rst_n,
input [3:0] in1,
input [3:0] in2,
output [8:0] out
);
genvar i;
reg [8:0]buff[3:0];
generate for(i=0;i<4;i=i+1) begin :loop
always@(posedge clk or negedge rst_n)
if(!rst_n)
buff[i]<=0;
else
buff[i]<=in2[i]?(in1<<i):0;
end
endgenerate
assign out=buff[0]+buff[1]+buff[2]+buff[3];
endmodule