`timescale 1ns/1ns
module seller2(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire sel ,
output reg out1,
output reg out2,
output reg out3
);
//*************code***********//
reg [2:0] money;
wire [2:0] charge;
assign charge = sel ? 5 : 3;
always@(posedge clk or negedge rst) begin
if(!rst) begin
money <= '0;
out1 <= '0;
out2 <= '0;
out3 <= '0;
end
else begin
if (money < charge) begin
money <= money + {d2, d1};
out1 <= 0;
out2 <= 0;
out3 <= 0;
end
else begin
money <= 0;
if (sel)
out2 <= 1;
else
out1 <= 1;
out3 <= money - charge;
end
end
end
//*************code***********//
endmodule