题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
parameter idle=4,s0=0,s1=1,s2=2,s3=3;
reg[2:0] cs,ns;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cs<=idle;
	end
	else begin
		cs<=ns;
	end
end
always@(*)begin
	if(!rst_n)begin
		ns=idle;
		match=0;
	end
	else begin
		case(cs)
		s0:begin
			ns=data_valid?(data?s1:s0):s0;
			match=0;
		end
		s1:begin
			ns=data_valid?(data?s2:s0):s1;
			match=0;
		end
		s2:begin
			ns=data_valid?(data?idle:s3):s2;
			match=0;
		end
		s3:begin
			ns=data_valid?(data?idle:s0):idle;
			match=1;
		end
		idle:begin
			ns=(data_valid& ~data)?s0:idle;
			match=0;
		end
		endcase

	end
end
  
endmodule