`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg data_reg;

always@(posedge clk or negedge rst)
    if(!rst)
        begin
            data_reg    <=  1'b0;
                q       <=  1'b0;
        end
    else
        begin            
            if(data)
            data_reg    <=  ~data_reg;
            if(data_reg)
                q       <=  ~q;
        end

//*************code***********//
endmodule