题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
    input [7:0]c,
	output [7:0]d
);
    wire[7:0] d1,d2;
    sub_mod inst1(.a(a),.b(b),.c(d1),.clk(clk),.rst_n(rst_n));
    sub_mod inst2(.a(a),.b(c),.c(d2),.clk(clk),.rst_n(rst_n));
    sub_mod inst3(.a(d1),.b(d2),.c(d),.clk(clk),.rst_n(rst_n));

endmodule

module sub_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,	
    output [7:0]c
);
    reg [7:0] c_reg;
    assign c = c_reg;
    always @(posedge clk or negedge rst_n)
        if(!rst_n)
            c_reg <= 0 ;
        else begin
            c_reg <= (a<b) ? a : b;
        end
        
endmodule