题解 | #格雷码计数器#

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg[3:0] gray_out
);
//格雷码转二进制
wire [3:0]bin_wire;
assign bin_wire={gray_out[3],gray_out[2]^bin_wire[3],gray_out[1]^bin_wire[2],gray_out[0]^bin_wire[1]};
//二进制相加
reg [3:0]bin;
always@(posedge clk or negedge rst_n)
begin if(!rst_n)
      bin<=0;
      else bin<=bin_wire+1;
end
//二进制转格雷码
always@(posedge clk or negedge rst_n)
begin if(!rst_n)
gray_out<=0;
else  gray_out<={bin[3],bin[2]^bin[3],bin[2]^bin[1],bin[0]^bin[1]};
end

endmodule