`timescale 1ns/1ns
module seller1(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire d3 ,
output reg out1,
output reg [1:0]out2
);
//====================================\\
//**************define sinals*********\\
//====================================\\
reg [6:0] cur_state ;
reg [6:0] nex_state ;
reg [2:0] coin ;
parameter S0 = 7'b0_000_001, // 0
S1 = 7'b0_000_010, // 0.5
S2 = 7'b0_000_100, // 1
S3 = 7'b0_001_000, // 1.5
S4 = 7'b0_010_000, // 2
S5 = 7'b0_100_000, // 2.5
S6 = 7'b1_000_000; // 3
//=====================================\\
//*****************main code***********\\
//=====================================\\
always@(posedge clk or negedge rst)begin
if(!rst)
coin <= 'd0 ;
else
coin <= {d1,d2,d3} ;
end
always@(posedge clk or negedge rst)begin
if(!rst)
cur_state <= S0 ;
else
cur_state <= nex_state ;
end
always@(*)begin
case(cur_state)
S0 : begin
if(coin == 3'b100)
nex_state = S1 ;
else if(coin == 3'b010)
nex_state = S2 ;
else if(coin == 3'b001)
nex_state = S4 ;
else
nex_state = S0 ;
end
S1 : begin
if(coin == 3'b100)
nex_state = S2 ;
else if(coin == 3'b010)
nex_state = S3 ;
else if(coin == 3'b001)
nex_state = S5 ;
else
nex_state = S1 ;
end
S2 : begin
if(coin == 3'b100)
nex_state = S3 ;
else if(coin == 3'b010)
nex_state = S4 ;
else if(coin == 3'b001)
nex_state = S6 ;
else
nex_state = S2 ;
end
default: nex_state = S0;
endcase
end
always@(posedge clk or negedge rst)begin
if(!rst)begin
out1 <= 1'b0 ;
out2 <= 'd0 ;
end
else begin
case(cur_state)
S0:begin
if(coin == 3'b001)begin
out1 <= 1'b1 ;
out2 <= 2'b01 ;
end
else begin
out1 <= 1'b0 ;
out2 <= 2'b00;
end
end
S1:begin
if(coin == 3'b010)begin
out1 <= 1'b1 ;
out2 <= 2'b00 ;
end
else if(coin == 3'b001)begin
out1 <= 1'b1 ;
out2 <= 2'b10;
end
else begin
out1 <= 1'b0 ;
out2 <= 2'b00;
end
end
S2:begin
if(coin == 3'b100)begin
out1 <= 1'b1 ;
out2 <= 2'b00 ;
end
else if(coin == 3'b010)begin
out1 <= 1'b1 ;
out2 <= 2'b01;
end
else if(coin == 3'b001)begin
out1 <= 1'b1 ;
out2 <= 2'b11;
end
else begin
out1 <= 1'b0 ;
out2 <= 2'b00;
end
end
default:begin
out1 <= 1'b0 ;
out2 <= 2'b00;
end
endcase
end
end
endmodule
采用米勒型状态机 输出不仅与当前状态有关还和输入有关。
注意点:1.输入是只有半个时钟周期的高电平 所以 三段式状态机 第二段的时候会有问题 因为第二段采用的组合逻辑 所以可以 给三个输入打一拍做一个处理
2. out2 是3bit 根据题目所述 找零0.5 所以 01 代表找零0.5元 10 代表1元 11 代表1.5元
3. 所以状态机一共有七个状态 分别代表 0 0.5 1 1.5 2 2.5 3 最多只能到3 因为 最多只能找零1.5元。

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