题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
parameter IDLE = 7'b0000001;
parameter S05  = 7'b0000010;
parameter S10  = 7'b0000100;
parameter S15  = 7'b0001000;
parameter S20  = 7'b0010000;
parameter S25  = 7'b0100000;
parameter S30  = 7'b1000000;

reg [6:0] cs, ns;
always @ (posedge clk or negedge rst) 
begin
    if( ~rst ) begin
        cs <= IDLE;
    end
    else begin
        cs <= ns;
    end 
end 

always @ (d1, d2, sel, rst, cs) 
begin
    if( ~rst ) begin
        ns = IDLE;
    end 
    else begin
        case( cs )
            IDLE : begin
                case({d1, d2}) 
                    2'b10 : ns = S05;
                    2'b01 : ns = S10;
                    default : ns = ns;
                endcase
            end 
            S05 : begin
                case({d1, d2}) 
                    2'b10 : ns = S10;
                    2'b01 : ns = S15;
                    default : ns = ns;
                endcase
            end 
            S10 : begin
                case({d1, d2}) 
                    2'b10 : ns = S15;
                    2'b01 : ns = S20;
                    default : ns = ns;
                endcase     
            end
            S15 : begin
                // 1.5 还是 2.5
                if(sel == 1'b0) begin
                    ns = IDLE;
                end
                else begin
                    case({d1, d2}) 
                        2'b10 : ns = S20;
                        2'b01 : ns = S25;
                        default : ns = ns;
                    endcase
                end 
            end
            S20 : begin
                // 1.5 还是 2.5
                if(sel == 1'b0) begin
                    ns = IDLE;
                end
                else begin
                    case({d1, d2}) 
                        2'b10 : ns = S25;
                        2'b01 : ns = S30;
                        default : ns = ns;
                    endcase
                end 
            end
            S25 : begin
                ns = IDLE; 
            end
            S30 : begin
                ns = IDLE;  
            end
            default : begin
                ns = IDLE;  
            end 
        endcase
    end 
end 

always @ (posedge clk or negedge rst) 
begin
    if( ~rst ) begin
        out1 <= 1'b0;
        out2 <= 1'b0;
        out3 <= 1'b0;
    end
    else begin
        case(ns) 
            IDLE : begin
                out1 <= 1'b0; 
                out2 <= 1'b0;
                out3 <= 1'b0;
            end 
            S05 : begin
                out1 <= 1'b0; 
                out2 <= 1'b0;
                out3 <= 1'b0;
            end 
            S10 : begin
                out1 <= 1'b0; 
                out2 <= 1'b0;
                out3 <= 1'b0; 
            end
            S15 : begin
                if(sel == 1'b0) begin
                    out1 <= 1'b1; 
                    out2 <= 1'b0;
                    out3 <= 1'b0; 
                end 
                else begin
                    out1 <= 1'b0; 
                    out2 <= 1'b0;
                    out3 <= 1'b0; 
                end 
            end
            S20 : begin
                if(sel == 1'b0) begin
                    out1 <= 1'b1; 
                    out2 <= 1'b0;
                    out3 <= 1'b1; 
                end 
                else begin
                    out1 <= 1'b0; 
                    out2 <= 1'b0;
                    out3 <= 1'b0; 
                end 
            end
            S25 : begin
                if(sel == 1'b0) begin
                    out1 <= 1'b0; 
                    out2 <= 1'd0;
                    out3 <= 1'b0; 
                end 
                else begin
                    out1 <= 1'b0; 
                    out2 <= 1'd1;
                    out3 <= 1'b0; 
                end 
            end
            S30 : begin
                if(sel == 1'b0) begin
                    out1 <= 1'b0; 
                    out2 <= 1'd0;
                    out3 <= 1'b0; 
                end 
                else begin
                    out1 <= 1'b0; 
                    out2 <= 1'd1;
                    out3 <= 1'b1; 
                end 
            end
            default : begin
                out1 <= 1'b0; 
                out2 <= 1'd0;
                out3 <= 1'b0;
            end 
        endcase
    end 
end

//*************code***********//
endmodule