题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//


reg  [16:0] d_reg;


always@(posedge clk or negedge rst)begin
    if(!rst)
        d_reg <= 'd0;
    else if(sel == 2'b0)
        d_reg <= d  ;
    else
        d_reg <= d_reg;
end


always@(posedge clk or negedge rst)begin
    if(!rst)begin
        out      <= 'd0;
        validout <= 1'b0;
    end
    else begin
        case(sel)
            2'd0: begin
                out      <= 'd0;
                validout <= 1'b0;
            end
            2'd1: begin
                out      <= d_reg[3:0]+d_reg[7:4];
                validout <= 1'b1;
            end
            2'd2: begin
                out      <= d_reg[3:0]+d_reg[11:8];
                validout <= 1'b1;
            end
            2'd3:begin
                out      <= d_reg[3:0]+d_reg[15:12];
                validout <= 1'b1;
            end
            default:;
        endcase
    end
end

//*************code***********//
endmodule