题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

always@(posedge clk or negedge rst_n )begin 
	if(!rst_n)
	ready_a<=0;
	else ready_a<=1;
end
reg [5:0]buff;
reg [2:0]cnt;
always@(posedge clk or negedge rst_n)begin 
	if(!rst_n)
      begin buff<=0;
	     cnt<=0;
		 data_b<=0;
		 valid_b<=0;
	  end
	  else if(valid_a)
	 begin   if(cnt==5)
	  begin cnt<=0;
	        data_b<={data_a,buff[5:1]};
			valid_b<=1;
	  end
	  else begin 
		   buff={data_a,buff[5:1]};
		   cnt<=cnt+1;
		   valid_b<=0;
	  end
	 end
end


endmodule