题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);

    wire [7:0] d_lest1;
	wire [7:0] d_lest2;
compare compare_1(
	.clk    (clk)         ,
	.rst_n  (rst_n)       ,
	.data_1 (a)           ,
	.data_2 (b)           ,
	.out    (d_lest1)
);




compare compare_2(
	.clk    (clk)         ,
	.rst_n  (rst_n)       ,
	.data_1 (a)           ,
	.data_2 (c)           ,
	.out    (d_lest2)
);

compare compare_3(
	.clk    (clk)         ,
	.rst_n  (rst_n)       ,
	.data_1 (d_lest1)           ,
	.data_2 (d_lest2)           ,
	.out    (d)
);
 

endmodule


module compare(
	input             clk          ,
	input             rst_n        ,
	input       [7:0] data_1       ,
	input       [7:0] data_2       ,
	output  reg [7:0] out
);
   always@(posedge clk or negedge rst_n)begin
       if(!rst_n)
	       out <= 'd0       ;
	   else if(data_1 <  data_2)
	       out <= data_1    ;
	   else
	       out <= data_2    ;
   end

endmodule