题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期


reg [6:0] cnt;
always @ (posedge clk_in or negedge rst) 
begin
    if( ~rst ) begin
        cnt <= 7'd0;
    end 
    else begin
        if(cnt == 7'd86) 
            cnt <= 7'b0;
        else
            cnt <= cnt + 7'b1;
    end 
end 

reg [2:0] cnt_8;
reg [3:0] cnt_9;
always @ (posedge clk_in or negedge rst) 
begin
    if( ~rst ) begin
        cnt_8 <= 3'd0;
        cnt_9 <= 4'd0;
    end 
    else begin
        if(cnt < c89) begin
            cnt_8 <= cnt_8 + 1'b1;       
        end
        else begin
            if(cnt_9 == div_o - 1)
                cnt_9 <= 4'd0;
            else 
                cnt_9 <= cnt_9 + 1'b1;     
        end
    end 
end

reg clk_o_r;
always @ (posedge clk_in or negedge rst) 
begin
    if( ~rst ) begin
        clk_o_r <= 1'b0;
    end 
    else begin
        if(cnt < c89) begin
            if(cnt_8 < 3'd4) 
                clk_o_r <= 1'b1;
            else
                clk_o_r <= 1'b0;       
        end
        else begin
            if(cnt_9 < 3'd4) 
                clk_o_r <= 1'b1;
            else
                clk_o_r <= 1'b0;       
        end
    end 
end

assign clk_out = clk_o_r;

//*************code***********//
endmodule