`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output [8:0] c
	);
    reg [8:0] a_tmp;
    reg [8:0] b_tmp;
    reg [8:0] c_tmp;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            a_tmp <= 0;
            b_tmp <= 0;
            c_tmp <= 0;
        end
        else begin
            a_tmp <= (a << 3) + (a << 2);
            b_tmp <= (b << 2) + b;
            c_tmp <= a_tmp + b_tmp;
        end
    end
    assign c = c_tmp;
    
endmodule