题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0] count_p; //上升沿计数
reg [2:0] count_n; //下降沿计数
reg clk_p;    //上升沿分频
reg clk_n;    //下降沿分频

//上升沿计数
always @ ( posedge clk_in or negedge rst )
begin 
 if( !rst ) 
  count_p <= 3'b0;
 else if( count_p == 3'd6 ) 
  count_p <= 3'b0;
 else  
  count_p <= count_p + 1'b1;
end

//上升沿分频
always  @ ( posedge clk_in or negedge rst )
begin 
 if( !rst ) begin 
  clk_p <= 1'b0;
 end 
 else begin 
  if( count_p == 3'd3 || count_p == 3'd6 ) begin 
   clk_p <= ~clk_p;
  end
 end
end

//下降沿计数
always @ ( negedge clk_in or negedge rst )
begin 
 if( !rst ) 
  count_n <= 3'b0;
 else if( count_n == 3'd6 ) 
  count_n <= 3'b0;
 else  
  count_n <= count_n + 1'b1;
end

//下降沿分频
always  @ ( negedge clk_in or negedge rst )
begin 
 if( !rst ) begin 
  clk_n <= 1'b0;
 end 
 else begin 
  if( count_n == 3'd3 || count_n == 3'd6 ) begin 
   clk_n <= ~clk_n;
  end
 end
end 

assign clk_out7 = clk_p | clk_n;


//*************code***********//
endmodule