`timescale 1ns/1ns module lca_4( input [3:0] A_in , input [3:0] B_in , input C_1 , output wire CO , output wire [3:0] S ); wire [3:0] g; wire [3:0] p; wire [4:0] c; assign g = A_in & B_in; //传播信号 assign p= A_in ^ B_in;//生成信号 assign c[0]=C_1; assign c[1]=g[0]|(p[0] & c[0] ); assign c[2]=g[1]|(p[1] & (g[0]|(p[0] & c[0] ))); assign c[3]=g[2]|(p[2]&(g[1]|(p[1] & (g[0]|(p[0] & c[0] ))))); assign c[4]=g[3]|(p[3] &(g[2]|(p[2]&(g[1]|(p[1] & (g[0]|(p[0] & c[0] ))))))); assign S=p^c[3:0]; assign CO=c[4]; endmodule
g是本级产生的
p是传播的
具体的在西安电子科技大学一个网课上有详细记载,
https://www.bilibili.com/video/BV19W4y1x7gr/?spm_id_from=333.337.search-card.all.click