题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0] out,
output reg validout
);
//*************code***********//

    reg    [15:0]    din;
    always @(posedge clk or negedge rst) begin
        if(!rst) begin
            out <= 5'd0;
            validout <= 1'b0;
            din     <=    16'd0;
        end
        else begin
            case(sel)
                2'd0: begin
                    out <= 5'd0;
                    din    <=    d;
                    validout    <=    1'b0;
                end
                2'd1: begin
                    out <= din[3:0] + din[7:4];
                    validout    <=    1'b1;
                end
                2'd2: begin
                    out <= din[3:0] + din[11:8];
                    validout    <=    1'b1;
                end
                2'd3: begin
                    out <= din[3:0] + din[15:12];
                    validout    <=    1'b1;
                end
            endcase
        end
    end
    
//*************code***********//