题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
reg [3:0] cnt1;
reg [3:0] cnt2;
wire flag1;
wire flag2;
wire [3:0]cnt;
assign cnt=cnt1+cnt2;
assign flag1=(!sel)&(cnt>=3)&(cnt1<5);
assign flag2=sel&(cnt>=5);
always@(posedge clk or negedge rst)begin 
	if(!rst)
	begin cnt1<=0;
	    cnt2<=0;
	end 
	 else if(flag1|flag2)
	 begin cnt1<=0;
	       cnt2<=0;
	end 
	else if(d1) cnt1<=cnt1+1;
	else if(d2) cnt2<=cnt2+2;
end
always@(posedge clk or negedge rst)begin 
	if(!rst)
	begin  out1<=0;
	  out2<=0;
	  out3<=0;
    end
	else if(sel)
	begin  if(flag2)
	  begin 
	  out1<=0;
	  out2<=1;
	  out3<=cnt1+cnt2-5;
	  end 
	  else 
	   begin  out1<=0;
	  out2<=0;
	  out3<=0;
    end
	end
	else if(flag1)
	  begin 
	  out1<=1;
	  out2<=0;
	  out3<=cnt1+cnt2-3;
	  end
	  else 
	  begin  out1<=0;
	  out2<=0;
	  out3<=0;
    end
    end

//*************code***********//
endmodule