`timescale 1ns/1ns

module sale(
   input                clk   ,
   input                rst_n ,
   input                sel   ,//sel=0,5$dranks,sel=1,10&=$drinks
   input          [1:0] din   ,//din=1,input 5$,din=2,input 10$
 
   output   reg  [1:0] drinks_out,//drinks_out=1,output 5$ drinks,drinks_out=2,output 10$ drinks
   output	reg        change_out   
);

parameter idle=0;//初始状态
parameter s0=1;  //选择A饮料,投入5元
parameter s1=2;  //选择A饮料,投入10元
parameter s2=3;  //选择B饮料,投入5元
parameter s3=4;  //选择B饮料,累计投入10元
parameter s4=5;  //选择B饮料,累计投入15元

reg[2:0] cs,ns;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)cs<=idle;
    else cs<=ns;
end

always@(*)begin
    case(cs)
        idle: ns=sel?(din==1?s2:din==2?s3:idle):(din==1?s0:din==2?s1:idle);
        s0:   ns=sel?(din==1?s2:din==2?s3:idle):(din==1?s0:din==2?s1:idle);
        s1:   ns=sel?(din==1?s2:din==2?s3:idle):(din==1?s0:din==2?s1:idle);
        s2:   ns=sel?(din==1?s3:din==2?s4:s2):s0;
        s3:   ns=sel?(din==1?s2:din==2?s3:idle):(din==1?s0:din==2?s1:idle);
        s4:   ns=sel?(din==1?s2:din==2?s3:idle):(din==1?s0:din==2?s1:idle);
        default: ns=idle;
    endcase
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        drinks_out<=0;
        change_out<=0;
    end
    else begin
        case(ns)
        idle:begin
            drinks_out<=0;
            change_out<=0;
        end
        s0:begin
            drinks_out<=1;
            change_out<=0;
        end
        s1:begin
            drinks_out<=1;
            change_out<=1;
        end
        s2:begin
            drinks_out<=0;
            change_out<=0;
        end
        s3:begin
            drinks_out<=2;
            change_out<=0;
        end
        s4:begin
            drinks_out<=2;
            change_out<=1;
        end
        default:begin
            drinks_out<=0;
            change_out<=0;
        end
        endcase

    end
end
endmodule