`timescale 1ns/1ns module seller1( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire d3 ,
output reg out1,
output reg [1:0]out2
); //**code//
reg [2:0] cnt1;
reg [1:0] cnt2;
reg cnt3;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
cnt1<=0;
cnt2<=0;
cnt3<=0;
end
else
begin
if(d1)
cnt1<=cnt1+1;
if(d2)
cnt2<=cnt2+1;
if(d3)
cnt3<=cnt3+1;
if(money >= 3) //如果用out1的话会迟1个clk
begin
cnt1<=0;
cnt2<=0;
cnt3<=0;
end
end
end
wire [3:0] money;
assign money = cnt1+{cnt2,1'b0}+{cnt3,2'b0};
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
out1<=0;
out2<=0;
end
else
begin
if(money >= 3)
begin
out1<=1;
out2<=money-3;
end
else
begin
out1<=0;
out2<=0;
end
end
end
//**code// endmodule