`timescale 1ns/1ns
module multi_pipe#(
parameter size = 4
)(
input clk ,
input rst_n ,
input [size-1:0] mul_a ,
input [size-1:0] mul_b ,
output reg [size*2-1:0] mul_out
);
reg [size*2-1:0] mul_a_t [size-1:0];
integer i;
integer j;
always @ (posedge clk or negedge rst_n)
begin
if(~rst_n) begin
for(i = 0; i < size; i = i+1) begin
mul_a_t[i] <= 'b0;
end
end
else begin
for(j = 0; j < size; j = j+1) begin
mul_a_t[j] <= mul_b[j] ? mul_a << j : 'b0;
end
end
end
reg [size*2-1:0] sum_t[size-1:0];
integer n;
always @ (*)
begin
for(n = 0; n < size; n = n+1) begin
if(n == 0)
sum_t[0] = mul_a_t[0];
else
sum_t[n] = sum_t[n-1] + mul_a_t[n];
end
end
always @ (posedge clk or negedge rst_n)
begin
if(~rst_n) begin
mul_out <= 'b0;
end
else begin
mul_out <= sum_t[size-1];
end
end
endmodule