`timescale 1ns/1ns
module width_24to128(
input clk ,
input rst_n ,
input valid_in ,
input [23:0] data_in ,
output reg valid_out ,
output reg [127:0] data_out
);
reg [3:0] COUNT ;
reg [119:0] data_out_reg ;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
COUNT <= 'd0 ;
else if(COUNT == 'd15 && valid_in == 1'b1)
COUNT <= 'd0 ;
else if(valid_in == 1'b1)
COUNT <= COUNT + 1'b1 ;
end
//缓存120bit的数据 也就是五个 data_in
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
data_out_reg <= 'd0 ;
else if( valid_in == 1'b1)
data_out_reg <= {data_out_reg[95:0], data_in};
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
data_out <= 'd0 ;
else if(COUNT == 'd5 && valid_in == 1'b1) // 24 24 24 24 24 8
data_out <= {data_out_reg, data_in[23:16]} ;
else if(COUNT == 'd10 && valid_in == 1'b1)
data_out <= {data_out_reg[111:0],data_in[23:8]} ; //{16 24 24 24},16
else if(COUNT == 'd15 && valid_in == 1'b1)
data_out <= {data_out_reg[103:0],data_in} ; //{8 24 24 24},24
else
data_out <= data_out ;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
valid_out <= 1'b0 ;
else if((COUNT == 'd5 | COUNT == 'd10 | COUNT == 'd15) && valid_in == 1'b1)
valid_out <= 1'b1 ;
else
valid_out <= 1'b0 ;
end
endmodule
非整数倍数据位宽转换 需要找到转换的规律
24 24 24 24 24 {8,16} 24 24 24 24 {16, 8} 24 24 24 24 24

京公网安备 11010502036488号